專任師資

周景揚 (Jou, Jing-Yang) 合聘教授/講座教授

 

工四館ED539
E-mail:jyjou@faculty.nctu.edu.tw
Tel:+886-3-5731850
Fax:+886-3-5750104

個人網頁:

實驗室網頁或詳細履歷:

電子設計自動化實驗室(Electronic Design Automation Lab)

學經歷

  • 行政院國家科學委員會副主任委員(02/2010-02/2012)
  • 台灣聯合大學系統副校長(教務)(04/2007-01/2010)
  • 國家實驗研究院國家晶片系統設計中心主任(02/2004-06/2007)
  • 台灣積體電路設計學會理事長(08/2006-07/2008)
  • 美國電機電子工程師學會會士(IEEE Fellow, 2005)
  • 電子工程系主任(08/2000-07/2003)
  • 交通大學電子工程學系特聘教授(02/2010-迄今)
  • 交通大學電子工程學系教授(1998-01/2010)
  • 交通大學電子工程學系副教授(1994-1998)
  • 美國AT&T貝爾實驗室研究員(1986-1994)
  • 美國吉悌電信公司(GTE)中央實驗室資深研究員(1985-1986)
  • 美國伊利諾大學香檳校區計算機科學博士(1985)
  • 美國伊利諾大學香檳校區電腦科學碩士 (1983)
  • 國立台灣大學電機工程學士(1979)
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研究方向

  • 電腦輔助設計
  • 積體電路與系統
  • 計算機結構

簡介

        Jing-Yang Jou received the B.S. degree in electrical engineering from National Taiwan University, Taiwan, R.O.C., and the M.S. and Ph.D. degrees in computer science from the University of Illinois at Urbana-Champaign, in 1979, 1983, and 1985, respectively.
        
        He was the Deputy Minister of National Science Council, Taiwan from February 2010 to February 2012. He was the Vice Chancellor (Academic Affairs), University System of Taiwan (consisting of four research universities: National Central University, National Chiao Tung University, National Tsing Hua University, and National Yang Ming University) from April 2007 to January 2010.He was the Executive Director of National SoC Program from April 2007 to January 2010. He was the Director General of National Chip Implementation Center, National Applied Research Laboratories in Taiwan from February 2004 to February 2007. He is a distinguished full Professor and was Chairman of Electronics Engineering Department from 2000 to 2003 at National Chiao Tung University, Hsinchu, Taiwan. Before joining Chiao Tung University, he was with GTE Laboratories from 1985 to 1986 and with AT&T Bell Laboratories at Murray Hill from 1986 to 1994.
        
        He received the distinguished paper award of the IEEE International Conference on Computer-Aided Design in 1990, the Outstanding Academy-Industry Cooperation Achievement Award granted by Ministry of Education (MOE), Taiwan, in 2002, and the Outstanding Electrical Engineering Professor Award from CIEE in 2006. His research interests include logic and physical synthesis, design verification, CAD for low power and Network on Chips. He has published more than 160 technical papers. Dr. Jou is a Fellow of IEEE.
        
        He was elected to the President of the Taiwan Integrated Circuit Design Society (TICD) 2007-2008. He serves as Associate Editor for IEEE Transactions on Very Large Scale Integration Systems from 2007 to 2010. He was the Technical Program Chairs of 2007 VLSI-DAT, the 12th VLSI Design/CAD Symposium (2001), and the Asia-Pacific Conference on Hardware Description Languages (APCHDL’97). He was the Honorary Chair of International Workshop on Multi-Project Chip (IWMC’06, 2006), and the Executive Chair of the 2nd Taiwan-Japan Microelectronics International Symposium (2002).