Chung, Shao-Shiun Steve

Steve S. Chung, Professor(莊紹勳 教授)

Engineering Building 4, Room 501

Lab room 411: 03-5712121 ext 54224

(mailing address)
Department of Electrical Eng. and Institute of Electronics
National Yang Ming Chiao Tung University (NYCU)
1001 University Road, Hsinchu 300
Tel: 886-3-573 1830


Current Position
  • NYCU Chair Professor/UMC Research Chair Professor
  • Ph.D. University of Illinois at Urbana-Champaign, 1985
Working Experience
  • IEEE VLSI-TSA, Executive Committee member (2022~)
  • IEEE Fellow Committee, member (2022~)
  • IEEE Silicon Nanoelectronics Workshop (SNW), General Chair (2022)
  • IEEE Symposium on VLSI Technology and Circuits, Executive Committee member (2020~)
  • Applied Physics A (Springer), Senior Editor (2020~)
  • IEEE Silicon Nanoelectronics Workshop (SNW), General Chair (2018)
  • IEEE Life Fellow (2018)
  • Research of Excellence Program, Ministry of Science and Technology, PI (2017~2019)
  • Applied Physics A (Springer), Editor (2017~2019)
  • IEEE EDS 50th WIMNACT workshop Chair, EDS Adcom mid-year meeting, May 2, 2016
  • IEEE IPFA Conference, General Chair, 2015
  • IEEE VLSI Technology and Circuits Committee, Focus Session Chair, 2014- 2015
  • IEEE EDS Elected Board of Governor (2012-2017)
  • IEEE EDS, Education Committee, Member, 2015-2018
  • IEEE Journal of EDS, Editor (2015~2019)
  • IEEE EDS Regions/Chapters-Asia Pacific, Chair (2013-2014)
  • International Solid State Devices and Materials Symposium (SSDM), JSAP, Organizing Committee member, (2010~)
  • Visiting Professor, University of California-Merced (2009.2- 2010.2)
  • Visiting Professor, Guest Instructor (graduate course), Stanford Univ. (2009 Fall)
  • Dean, Office of International Affairs, NCTU (2007/9/20- 2008/7/31)
  • Executive Director, NCTU Top-University Plan (2007/2/1~ 2007/9/20)
  • NCTU Chair Professor (2006.2 ~)
  • IEEE Fellow (2006)
  • UMC Research Chair Professor (2005 ~)
  • Department Head, EECS Undergraduate Honors Program (2004-2005)
  • Visiting Scholar, Stanford University (2001-2002)
  • Full Professor, NCTU (1989 ~ 2006)
  • Associate Professor, NCTU (1987-1989)
  • IEEE EDS Ex-Officio Member
  • IEEE EDS Elected AdCom Member (2 terms, 2007-2009)
  • IEEE Taipei Section Board Member (2 terms, 2007 ~ 2008)
  • IEEE Taipei Section Board Member (2005 ~ 2006)
  • SSDM(International Solid State Devices and Materials Symposium), Technical Program Vice-Chair, 2007-2009
  • IEEE 6th WIMNACT Workshop Chair (2005)
  • IEEE EDS Graduate Student Fellowship Committee Member (2005 ~)
  • IEEE EDS Elected AdCom Member  (2004-2006)
  • IEEE EDS Regions/Chapters-AP Vice Chair /chair (2004 ~2009)
  • IEEE ICMTS conference, TPC Member (2005-2007)
  • IEEE VLSI Technology and Circuit Committee, member (2004 ~)
  • EDMS(Electron Devices and Materials Symposium), Technical Program Chair (2004)
  • Guest Editor, IEEE TDMR Journal (2004)
  • IEEE SMTW, workshop Technical Program, Co-Chiar (2004)
  • IEEE IPFA Technical Program Chair (2004)
  • IEEE VLSI-TSA, Taiwan-Committee Chair (2003)
  • IEEE Distinguished Lecturer (2002 ~)
  • IEEE EDL Editor (2002 ~ 2008)
  • IEEE EDS Taipei Chapter, Chair (2000 ~2010))
  • IEEE IEDM Committee Member, Session Chair (2003-2004)
  • IEEE IRPS Committee Member, Session Chair (2003-2004)
  • IEEE Symposium on VLSI Technology, Committee Member, session Chair (2000 ~)
  • TSMC Consultant (1993- 1999)
  • MOSEL Consultant (1992)
  • Research Assistant, Illinois Solid State Electronics Lab- Prof. C. T. Sah (CMOSco-inventor) group (1983-1985)
Research Interests
  • Advanced CMOS Device Technology and Reliability
  • Resistance Memory Technology and Circuits
  • AI and Network Security Chip

  Steve S. Chung received his Ph.D. degree from the University of Illinois at Urbana-Champaign, in Electrical Engineering in 1985. His Ph.D.thesis advisor is the world-famous scholar and CMOS Co-Inventor, Prof. C. T. Sah.

        Currently, he is an NYCU(NCTU) Chair Professor, UMC Research Chair Professor at the National Chiao Tung University (NCTU), where he worked as Dean of International Affairs,between 2007-2008. Between 2004-2005, he was the first Department Head of EECS Honors Program, to promote a new undergraduate program for academic excellence, at NCTU where he has served since 1987. He was a Visiting Professor with the University of California-Merced(2009-2010), a guest Instructor at Stanford (2009) and also a visiting scholar to Stanford University, CA, in 2001. He was also the consultant to both TSMC and UMC on developing CMOS and flash memory technologies. His current research areas include CMOS device technology with emphasis on trigate and Tunneling FET, flash memory technology, resistance memory technology,embedded memory technology, reliability characterization and modeling. He has published more than 300 journal and conference papers, one textbook, and holds more than 40 patents. Since 1995, he has personally presented more than 35 times in the world leading IEEE conferences, IEDM and VLSI, with focus on the reliability and technology of advanced-CMOS, flash memory, resistance memory etc. In particular, he is the first (from Taiwan) to present the paper at VLSI Technology symposium in 1995. Three highest impact inventions (with both paper publishing and patents) by his team includes: (1) IFCP(Incremental Frequency Charge Pumping)[1], a milestone for the CMOS reliability analysis beyond the 90nm generation. This method can replace the conventional CV method (which has been used for 50 years) in measuring the interface/oxide traps with small dimensions and with gate oxide thickness in the tunneling regime. (2) A unique Ig-RTN transient measurement on the understanding of FET breakdown based on the characterization of traps in the gate dielectric. A third breakdown was discovered [2], different from the well known soft-breakdown and hard-breakdown. This led to the invention of an OTP structure [3] with vast economic benefit. (3) A new invention of one-transistor nonvolatile memory [4] which will be able to replace conventional Floating Gate since its inception in 1967, as floating gate reaches its scaling limit at around 20nm. These are cornerstones for a sustainable semiconductor industry when the Silicon technology scaling is continuing.

        He is an IEEE Fellow, IEEE EDS BoG(Board Governor) member (2014-2016), EDS AdCom member (2004-2009), IEEE Distinguished Lecturer, EDS Regions/Chapters Vice-Chair/Chair, and Editor of J-EDS (2014-), Editor of EDL(2002-2008). He has served on the committees of premiere conferences, e.g., VLSI Technology, IEDM, IRPS, etc. Also, he has been the Technical Program Chair of 2004 and 2015 IPFA, the Technical Program Vice-Chair of SSDM (the largest conference in semiconductor areas in Japan). ED Taipei chapter was awarded the 2002 EDS Chapter of the Year Award under his leadership as the chapter chair. This is a remarkable achievement and milestone to the IEEE societies in Taiwan since the chapter is the first one to receive this honor among those 26 IEEE Taipei chapters at that time. He was awarded 3 times outstanding Research Award for excellence in research, as well as the top-PI in 2003, and the current distinguished NSC Research Fellow, from the National Science Council. He was also granted Distinguished EE Professor and Engineering Professor by the Engineering Societies of Taiwan.
        He was the recipient of 2013 Pan Wen Yuan award in recognizing his outstanding achievements in the semiconductor research.    

[1] S.S. Chung; S.-J. Chen; C.-K. Yang; S.-M. Cheng et al., “A novel and direct determination of the interface traps in sub-100 nm CMOS devices with direct tunneling regime (12~16 A) gate oxide,” Symp. VLSI Tech., 2002. DOI: 10.1109/VLSIT.2002.1015394
[2] S. S. Chung, “The discovery of a third breakdown: phenomenon, characterization and applications,” Applied Physics-A, Jan. 17, 2023
[3] S. S. Chung et al., Dielectric Fuse Memory Circuit and Operation Method Thereof, US patent No. 10,127,993,
November 13, 2018.
[4] S. S. Chung, E. R. Hsieh, S. P. Yang, and C. H. Chuang, “ A Novel One-Transistor Resistance-Gate Nonvolatile
Memory,” 74th Device Research Conference, Delaware, pp. 251-252, June 19-22, 2016.

Honors/Awards & Major Achievements 

2021 VLSI Technology Symposium, Demo session paper (final list), 2021.6
IEEE IEDM, Highlight paper, 2020 [5]
IEEE Journal of Electron Devices, Editor Service Award, 2019
2019 VLSI Technology Symposium, Demo session paper (final list), 2019.6
Lifetime Achievement Award of National Inventors (2019)
IEEE Life Fellow, 2018
Lifetime Contribution Award, Taiwan Electron Devices and Materials Association, 2018
Y.Z. You-Hsiang Scientific Paper, 2018.8
2017 VLSI Technology Symposium, Highlight paper [6]
Pan Wen-Yuan Outstanding Research Award, 2013
NSC Distinguished research Fellow, 2013~
NSC Distinguished Research Fellow, 2009-2012
IEEE Fellow (for contributions to the reliability of ultra-thin-oxide CMOS devices), 2006
NSC Outstanding Research Fellow, 2006-2009
Outstanding Research Award (Three times), 1996-2003
Excellent Research Award (Three times), 1989-1995
Distinguished Engineering Professor), Chinese Electrical Engineering Society
Distinguished EE Professor, Chinese Engineers Society

[5] W. Y. Yang, B. Y. Chen, C. C. Chuang, E. R. Hsieh, K. S. Li, and S. S. Chung, “Novel Concept of Hardware Security in Using
Gate-switching FinFET Nonvolatile Memory to Implement True-Random-Number Generator,” in IEDM Tech. Dig., San Francisco CA, Dec. 12-16, 2020.
(see report in Nature Electronics, by C. Varnava, FinFETS for Cryptography, Dec. 11, 2020, https://www.nature.com/articles/s41928-020-00521-5
[6] E. R. Hsieh, S. S. Chung et al., “First Demonstration of Flash RRAM on Pure CMOS Logic 14nm FinFET Platform Featuring Excellent Immunity to Sneak-path and MLC Capability,” in Symposium on VLSI Technology, pp. 64-65, Kyoto, June 13-17, 2017. A world first FinFET Resistance NVM feasible for embedded memory in advance 14nm platform (A highlight paper)

Patents: > 40
Published papers : IEEE Journal and Conference Papers (more than 300)  

IEDM/VLSI: ~35 (as First author) (up to 2022.12)
1995 VLSI Technology (The first paper contributed from Taiwan)
1997 VLSI Technology (The only paper contributed from Taiwan) [7]
1995-2016 VLSI Technology (37% of contributed papers by Taiwan authors- in Academia)
2002 IEEE EDS Chapter of the Year Award (as the IEEE EDS Taipei Chapter chair)
IRPS Best poster paper award, 2020   
IEDMS Best Paper Award (2020)   
IEDMS Best Paper Award (2010)    
IEDMS Best Paper Award (1996)

[1] S. S. Chung et al., in Symposium on VLSI Tech., pp. 74-75, Hawaii, 2002. ( also, US patent, No. 6,746,883)
[7] S. S. Chung et al., in Symposium on VLSI Tech., pp. 111-112, Kyoto, 1997.

Who’s who in the world, 1999, 2000, 2001 Editions
Who’s who in finance, 2000 Edition
Who’s who in Asia, 2006 Edition        

Lab. Website or Detailed C.V.
Emerging Device and Technology Lab

  • Undergraduate level:
    • Electronics
    • Circuit Theory
  • Physics of Semiconductor Devices
  • Graduate level:
    • Special Topics on VLSI Devices and Technology
    • Flash Memory Devices and Technology