Faculty

Su, Pin

蘇彬(Pin Su)

Office: ED531; Tel: 886-3-5712121 ext.54142
E-mail: pinsu@faculty.nctu.edu.tw

個人網頁:

實驗室網頁或詳細履歷:

著作列表 (Publication List)

學經歷

  • 美國加州柏克萊大學電機工程博士
  • 國立交通大學電子工程學系教授

研究方向

  • Modeling, Design and Evaluation of Exploratory/Beyond-CMOS Devices for Logic and Memory Applications. These devices include FinFET/Multigate transistors, Stacked Nanowire/Nanosheet, High-Mobility III-V/Ge Channel devices, 2D-Material transistors, Negative-Capacitance FETs, Ferroelectric FETs, etc.

授課內容

  • 矽奈米元件及物理 (研, Spring 2019)
  • 計測實驗 (研, Spring 2020)
  • 半導體元件物理 (大三, Fall 2019)
  • 半導體基礎理論 (大二, Spring 2020)

簡介

        Pin Su has been a professor of EE at National Chiao Tung University since 2003. He received PhD degree from the Department of Electrical Engineering and Computer Sciences, University of California at Berkeley in 2002.
        Prof. Su has received teaching awards from National Chiao Tung University in 2015 (EE college level) and 2019 (University level), respectively. He has supervised 10 PhD dissertations in solid-state electronics. His research interests include silicon-based nanoelectronics, modeling and design for exploratory/beyond CMOS devices, and circuit-device interaction and co-optimization for low-power logic and memory applications. His research work has been disseminated through over 100 refereed journal papers and over 180 conference papers and invited talks.
        Prof. Su has served as the technical committee member of IEDM (2012-2013), SSDM (2016-present) and EDTM (2017-2018), among others.